---------------------------------------------------------------------------------
  -- Design Name : Adder
  -- File Name   : GenAdd32.vhd
  -- Function    : Defines simple 32b adder
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity GenAdd32 is
  port (
    in1:      in  word32;
    in2:      in  word32;
    add_out:  out word32 := (others => '0');
    v:        out std_logic := '0';
    c:        out std_logic := '0'
  );
end GenAdd32;

architecture behavioral of GenAdd32 is
  signal result : word32;
  signal resultExt : word32Ext;
begin
  resultExt <= std_logic_vector(unsigned('0' & in1) + unsigned('0' & in2));
  result <= resultExt(result'left downto 0);
  
  c <= resultExt(resultExt'left);                                                                  -- carry flag
  
  v <= (not in1(in1'left) and not in2(in2'left) and     result(result'left)) or                    -- overflow flag
       (    in1(in1'left) and     in2(in2'left) and not result(result'left));                
  
  add_out <= result;

end architecture behavioral;